The IEEE 1149.1 test access port (TAP) and boundary scan architecture, which is commonly referred to as JTAG, is a popular testing and device programming scheme. JTAG is an acronym standing for the Joint Test Action Group, which is a technical subcommittee that was initially responsible for developing the standard. Many electronic devices are available that comply with the IEEE 1149.1 standard. For example, many Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD) and memory devices such as Flash and other EEPROM devices include a JTAG Test Access Port (TAP) and can be programmed, configured, tested and verified through the port. Furthermore, the boundary scan architecture provides for the testing of interconnections between two or more JTAG compatible devices. Therefore, the JTAG or IEEE 1149.1 standard provides a means to ensure the integrity of individual board level components as well as board level interconnections. Boundary scan tests are commonly used to detect opens and shorts at both the board and individual device level, thereby reducing the need for expensive bed-of-nails testing.
The standard requires that a Test Access Port support at least a set of four signals. The signals are named Test Data In (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). Optionally, a Test Reset Signal (TRST) may also be supported. Referring to FIG. 1, generally a piece of illustrative electronic JTAG compliant hardware 110 includes a plurality of JTAG compliant devices 114. TDO and TDI pins of the devices are interconnected in a boundary scan chain 118. The electronic hardware 110 includes a board level Test Access Port 122. The board level Test Access Port 122 is connected to the Test Access Ports of the individual devices 114. A JTAG source 126 is shown connected to the board level JTAG port. For example, the JTAG source 126 is a piece of Automatic Test Equipment (ATE) used in the manufacturing process, a personal computer, or some other specialized piece of hardware adapted to manipulate and control the TAP signals. Because the Test Data In (TDI) and the Test Data Out (TDO) pins of the JTAG compliant devices are connected in the boundary scan chain 118, the JTAG source can send commands to and receive results from each of the JTAG compliant devices 114. Therefore, a JTAG source can program, configure, verify or test a plurality of JTAG compliant devices at once.
More specifically, a piece of JTAG compliant hardware can include a plurality of specialized devices. The plurality can include both JTAG compliant and non-compliant devices. For instance, a piece of compliant hardware can include a boot processor. A boot processor can configure devices associated with the hardware when the hardware is powered up. For example, the configuration can be based on information stored in a memory device of the electronic hardware. The boot processor can be the main, or only, processor of the electronic device. For instance, a main processor is placed in boot processor mode when the electronic device is powered up. When the boot process is completed, the main processor reverts to a main processor function. Alternatively, the boot processor can be dedicated to the booting function. In this case, a second processor is responsible for the main functions of the electronic device.
Referring to FIG. 2 for purposes of a more detailed illustration, a second piece of JTAG compliant electronic hardware 210 includes a boot processor 214 and a high-speed processor 218. The boot processor includes a JTAG port 222. The boot processor 214 communicates with other devices over a boot bus 226. The high-speed processor 218 communicates with other devices over a high-speed bus 230. A bridge 234 allows the boot processor 214 to communicate with devices on the high-speed bus 230. For example, the boot processor communicates with boot Flash 238, boot RAM 242 and the bridge 234 over the boot bus 226. For instance, the boot Flash 238 and boot RAM 242 might be non-compliant devices.
The high-speed processor 218 communicates with a cache 246 over a cache bus 248. The high-speed processor 218 communicates with a large RAM 250, I/O and status registers 254, peripherals 258 and a Flash/ROM 262 over the high-speed bus 230.
The JTAG port 222 communicates with a boundary scan chain 266 including the bridge 234, the cache 246, the high-speed processor 218, the large RAM 250, the I/O and status registers 254, the Flash/ROM 262, and the peripherals 258.
On power up, the boot processor can read configuration, programming, verification or test information from the boot flash 238. The boot processor 214 controls the JTAG port 222 to communicate with the boundary scan chain 266. The boot processor configures, programs, verifies or tests the devices 234, 246, 218, 250, 254, 258, 262 on the boundary scan chain 266, as directed by the information stored in the boot Flash 238.
Programming, configuring, verifying and testing hardware such as the exemplary hardware of FIG. 1 and FIG. 2 can be expensive.
Referring to FIG. 3, currently there are at least three methods for using JTAG vectors with electronic devices of a piece of electronic hardware 302. In one method, a JTAG source such as Automatic Test Equipment (ATE) 304 is loaded with JTAG vector information. For example, the ATE is loaded with boundary scan test vectors 306 for testing board level interconnections. The boundary scan test vectors are generated by development and test support software running on, for example, a host computer 307. The Automatic Test Equipment 304 is connected to the piece of electronic hardware 302. The connection is either a direct connection to Test Access Port signal lines of the electronic hardware 302 (see 122 of FIG. 1) or an indirect connection through a JTAG access port interface 308. The Automatic Test Equipment 304 manipulates and monitors the Test Access Port signals (TDI, TDO, TMS, TCK and optionally TRST) according to the JTAG vectors, in order to control and monitor the inputs and outputs of electronic devices 310 as a means for testing printed circuit board traces and other device interconnections. Alternatively, or additionally, the ATE 304 can be loaded with programming, configuration, or test vectors 312 and used to program, configure, validate and/or test the devices 310 after they are installed in the electronic hardware 302.
In another method, a device programmer 330 is loaded with JTAG programming, configuration and/or test vector information 312 and used to program electronic devices 314 prior to the installation of the devices 314 in the piece of electronic hardware 302.
In a third method, only a boot EEPROM 334 is programmed by a device programmer 338. The EEPROM 334 is installed in the electronic hardware 302. A boot processor 342 of the electronic hardware 302 has access to the test access port signal lines of JTAG compatible devices (e.g., devices 310) on the electronic hardware 314. The boot processor 342 reads the information stored in the EEPROM 334 and manipulates and monitors the Test Access Port signal lines to program, configure, verify and/or test the JTAG compatible devices and interconnections associated therewith according to the read information.
All of these methods for programming, configuring, verifying and/or testing the electronic hardware 302 and devices 310, 314, 334 associated therewith require the use of expensive and complicated equipment such as the automatic test equipment 304 and device programmers 330, 338. Additionally, the methods require trained technicians to operate the equipment 304, 330, 338, and where necessary, install devices 314, 334. Therefore, these methods can be useful in a product or electronic hardware 314 development environment, where the cost of equipment 304, 330, 338 and technician training can be amortized over a great number of pieces of electronic hardware 302. However, these methods become prohibitively expensive once the electronic hardware 302 has been installed in a customer's site. For example, where an electronic device 302 is installed at a customer's site and requires testing or updating, it can be impractical to send automatic test equipment, device programmers and trained technicians to the customer's site to do the testing or updating.
Therefore, there is a desire for a system and method for programming, configuring, verifying and/or testing a piece of electronic hardware remotely. This remote capability eliminates transportation costs, simplifies scheduling and reduces a number of skilled technicians required to service an installed base of electronic devices.